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application note AN4134 design guidelines for off-line forward converters using fairchild power switch (fps tm ) www.fairchildsemi.com ?2003 fairchild semiconductor corporation abstract this paper presents practical design guidelines for off-line forward converter employing fps (fairchild power switch). switched mode power supply (smps) design is inherently a time consuming job requiring many trade-offs and iteration with a large number of design variables. the step-by-step design procedure described in this paper helps the engineers to design a smps easily. in order to make the design process more efficient, a software design tool, fps design assistant, that contains all the equations described in this paper, is also provided. rev. 1.0.0 1. introduction due to circuit simplicity, the forward converter has been widely used for low to medium power conversion applications. figure 1 shows the schematic of the basic off- line forward converter using fps, which also serves as the reference circuit for the design procedure described in this paper. because the mosfet and pwm controller together with various additional circuits are integrated into a single package, the design of smps is much easier than the discrete mosfet and pwm controller solution. this paper provides step-by-step design procedure for an fps based off-line forward converter, which includes transformer design, reset circuit design, output filter design, component selection and closing the feedback loop. the design procedure described herein is general enough to be applied to various applications. the design procedure presented in this paper is also implemented in a software design tool (fps design assistant) to enable the engineer to finish smps design in a short time. in the appendix, a step-by-step design example using the software tool is provided. np n s1 + v dc - ac line d r1 c o1 drain vcc gnd fb fps ntc fuse r l1 c l1 line filter c l2 n a d a r a c a ka431 817a r d r bias r 1 r 2 r f c f bridge rectifier diode v o1 l 1 c b 2c dc n s2 d r2 v o2 l 2 d f2 d f1 c o2 2c dc non-doubled doubled reset circuit c p1 l p1 c p2 l p2 figure 1. basic off-line forward converter using fps
AN4134 application note 2 ?2002 fairchild semiconductor corporation 2. step-by-step design procedure in this section, design procedure is presented using the schematic of the figure 1 as a reference. in general, most fps has the same pin configuration from pin 1 to pin 4, as shown in figure 1. (1) step-1 : determine the system specifications - line voltage range ( v line min and v line max ) : usually, voltage doubler circuit as shown in figure 1 is used for a forward converter with universal input. then, the minimum line voltage is twice the actual minimum line voltage. - line frequency ( f l ). - maximum output power ( p o ). - estimated efficiency ( e ff ) : it is required to estimate the power conversion efficiency to calculate the maximum input power. if no reference data is available, set e ff = 0.7~0.75 for low voltage output applications and e ff = 0.8~0.85 for high voltage output applications. with the estimated efficiency, the maximum input power is given by considering the maximum input power, choose the proper fps. since the voltage stress on the mosfet is about twice the input voltage in the case of the forward converter, an fps with 800v rated mosfet is recommended for universal input voltage. the fps lineup with proper power rating is also included in the software design tool. (2) step-2 : determine dc link capacitor (c dc ) and the dc link voltage range. the maximum dc link voltage ripple is obtained as where d ch is the dc link capacitor charging duty ratio defined as shown in figure 2, which is typically about 0.2. it is typical to set ? v dc max as 10~15% of for voltage doubler circuit, two capacitors are used in series, each of which has capacitance twice of the capacitance that is determined by equation (2). with the resulting maximum voltage ripple, the minimum and maximum dc link voltages are given as figure 2.dc link voltage waveform (3) step-3 : determine the transformer reset method and the maximum duty ratio (d max ) one inherent limitation of the forward converter is that the transformer must be reset during the mosfet off period. thus, additional reset schemes should be employed. two most commonly used reset schemes are auxiliary winding reset and rcd reset. according to the reset schemes, the design procedure is changed a little bit. (a) auxiliary winding reset : figure 3 shows the basic circuit diagram of forward converter with auxiliary winding reset. this scheme is advantageous in respect of efficiency since the energy stored in the magnetizing inductor goes back to the input. however, the extra reset winding makes the construction of the transformer more complicated. figure 3. auxiliary winding reset forward converter p in p o e ff ------ - = (1) ? v dc max p in 1 d ch ? () ? 2v line min 2f l c dc ?? ------------------------------------------------------------ = (2) 2v line min v dc min 2v line min ? v dc max ? = (3) v dc max 2v line max = (4) dc link voltage dc link voltage ripple t 1 t 2 d ch = t 1 / t 2 = 0.2 - 0.25 nr np ns l v dc vo vgs on on vds v dc i m v in n p /n r r p oss m dc n n c l v / t 0 t 3 t 2 t 1 t 4 i m i m- i m+ t 5 i r i r + vds - l m vgs d reset
application note AN4134 3 ?2002 fairchild semiconductor corporation the maximum voltage on mosfet and the maximum duty ratio are given by where n p and n r are the number of turns for the primary winding and reset winding, respectively. as can be seen in equations (5) and (6), the maximum voltage on the mosfet can be reduced by decreasing d max . however, decreasing d max results in increased voltage stress on the secondary side. therefore, it is proper to set d max =0.45 and n p = n r for universal input. for auxiliary winding reset, fps, of which duty ratio is internally limited below 50%, is recommended to prevent core saturation during transient. (b) rcd reset : figure 4 shows the basic circuit diagram of the forward converter with rcd reset. one disadvantage of this scheme is that the energy stored in the magnetizing inductor is dissipated in the rcd snubber, unlike in the reset winding method. however, due to its simplicity, this scheme is widely used for many cost-sensitive smps. figure 4. rcd reset forward converter the maximum voltage stress and the nominal snubber capac- itor voltage are given by since the snubber capacitor voltage is fixed and almost independent of the input voltage, the mosfet voltage stress can be reduced compared to the reset winding approach when the converter is operated with a wide input voltage range. another advantage of rcd reset method is that it is possible to set the maximum duty ratio larger than 50% with relatively low voltage stress on the mosfet compared to auxiliary winding reset method, which results in reduced voltage stress on the secondary side. (4) step-4 : determine the ripple factor of the output inductor current. figure 5 shows the current of the output inductor. the ripple factor is defined as where i o is the maximum output current. for most practical design, it is reasonable to set k rf =0.1~ 0.2. figure 5. output inductor current and ripple factor once the ripple factor is determined, the peak current and rms current of mosfet are obtained as check if the mosfet maximum peak current ( i ds peak ) is below the pulse-by-pulse current limit level of the fps ( i lim ). v ds max v dc max 1 n p n r ------ - + ?? ?? = (5) d max n p n p n r + ------------------- - (6) - v sn + ns l v dc vo vgs on on vds v dc i m v sn oss m sn c l v / t 0 t 3 t 2 t 1 t 4 i m i m- i m+ t 5 i sn l m np r sn i sn vgs + vds - d reset v ds max v dc max = v sn + (7) v sn v dc min d max ? 1 d max ? () --------------------------------------- - > (8) k rf ? i 2i o ------- - = (9 ) i ? o i o rf i i k 2 ? = t s dt s i ds peak i edc 1k rf + () = (10) i ds rms i edc 3k rf 2 + () d max 3 ------------- - = (11) where i edc p in v dc min d max ? ------------------------------------- - = (12)
AN4134 application note 4 ?2002 fairchild semiconductor corporation (5) step-5 : determine the proper core and the minimum primary turns for the transformer to prevent core saturation. actually, the initial selection of the core is bound to be crude since there are too many variables. one way to select the proper core is to refer to the manufacture's core selection guide. if there is no proper reference, use the following equation as a starting point. where a w is the window area and a e is the cross sectional area of the core in mm 2 as shown in figure 6. f s is the switching frequency and ? b is the maximum flux density swing in tesla for normal operation. ? b is typically 0.2-0.3 t for most power ferrite cores in the case of a forward converter. notice that the maximum flux density swing is small compared to flyback converter due to the remnant flux density. figure 6. window area and cross sectional area with a determined core, the minimum number of turns for the transformer primary side to avoid saturation is given by (6) step-6 : determine the number of turns for each inding of the transformer first, determine the turns ratio between the primary side and the feedback controlled secondary side as a reference. where n p and n s1 are the number of turns for primary side and reference output, respectively. v o1 is the output voltage and v f1 is the diode forward voltage drop of the reference output. then, determine the proper integer numbers for n s1 so that the resulting n p is larger than npmin obtained from equation (14). the magnetizing inductance of the primary side is given by where a l is the al-value with no gap in nh/turns 2 . the numer of turns for the n-th output is determined as where v o(n) is the output voltage and v f(n) is the diode forward voltage drop of the n-th output. the next step is to determine the number of turns for vcc winding. the number of turns for vcc winding is determined differently according to the reset method. (a) auxiliary winding reset : for auxiliary winding reset, the number of turns of the vcc winding is obtained as where vcc* is the nominal voltage for vcc and v fa is the diode forward voltage drop. since vcc is proportional to the input voltage when auxiliary winding reset is used, it is proper to set vcc* as the vcc start voltage to avoid the over voltage protection during the normal operation. (b) rcd reset : for rcd reset, the number of turns of the vcc winding is obtained as where vcc* is the nominal voltage for vcc. since vcc is almost constant for rcd reset in normal operation, it is proper to set vcc* to be 2-3 v higher than vcc start voltage. (7) step-7 : determine the wire diameter for each transformer winding based on the rms current. the rms current of the n-th winding is obtained as where i o(n) is the maximum current of n-th output. a p a w a e = 11.1 p in 0.141 ? b f s ?? ------------------------------------- 1.31 10 4 mm 4 () = 13 () aw aw aw aw ae ae ae ae n p min v dc min d max ? a e f s ? b ?? ------------------------------------- - 10 6 = turns () 14 () n n p n si -------- v dc min d max ? v o1 v f1 + ------------------------------------- - == (15 ) l m a l n p 2 10 9 ? (h) = (16) n s n () v o n () v f n () + v o1 v f1 + --------------------------------- - n s1 (turns) ? = (17 ) n a v cc *v fa + v dc min --------------------------- - n r (turns) ? = (18) n a v cc *v fa + v sn --------------------------- - n p (turns) ? = (19) i n () sec rms i on () 3k rf 2 + () d max 3 ------------- - = (20)
application note AN4134 5 ?2002 fairchild semiconductor corporation when the auxiliary winding reset is employed, the rms cur- rent of the reset winding is as follows. the current density is typically 5a/mm 2 when the wire is long (>1m). when the wire is short with small number of turns, current density of 6-10 a/mm 2 is also acceptable. avoid using wire with a diameter larger than 1 mm to avoid severe eddy current losses and to make winding easier. for high current output, it is better to use parallel winding with multiple strands of thinner wire to minimize skin effect. check if the winding window area of the core is enough to accommodate the wires. the required window area is given by where a c is the actual conductor area and k f is the fill factor. typically the fill factor is 0.2-0.3 when a bobbin is used. (8) step-8 : determine the proper core and the number of turns for output inductor when the forward converter has more than one output as shown in figure 7, coupled inductors are usually employed to improve the cross regulation, which are implemented by winding their separate coils on a single, common core. figure 7. coupled output inductors first, determine the turns ratio of the n-th winding to the reference winding (the first winding) of the coupled inductor. the turns ratio should be the same with the transformer turns ratio of the two outputs as follows. then, calculate the inductance of the reference output inductor as the minimum number of turns for l 1 to avoid saturation is given by where i lim is the fps current limit level, a e is the cross sectional area of the core in mm 2 and b sat is the saturation flux density in tesla. if there is no reference data, use b sat =0.35-0.4 t. once n l1 is determined, n l(n) is determined by equation (23). (9) step-9 : determine the wire diameter for each inductor winding based on the rms current. the rms current of the n-th inductor winding is obtained as the current density is typically 5a/mm 2 when the wire is long (>1m). when the wire is short with small number of turns, a current density of 6-10 a/mm 2 is also acceptable. avoid using wire with diameter larger than 1 mm to avoid severe eddy current losses and to make winding easier. for high current output, it is better to use parallel winding with multiple strands of thinner wire to minimize skin effect. (10) step-10 : determine the diode in the secondary side based on the voltage and current ratings. the maximum voltage and the rms current of the rectifier diode of the n-th output are obtained as (11) step-11 : determine the output capacitor considering the voltage and current ripple. the ripple current of the n-th output capacitor is obtained as i reset rms v dc min d max l m f s ---------------------------------------- d max 3 ------------- - = (21) a w a c k f ? = (22) np n s1 d r1 c o1 v o1 l 1 n s2 d r2 v o2 l 2 d f2 d f1 c o2 n l2 n l1 n s n () n s1 ------------- n l n () n l1 ------------- = (23) l 1 v o1 v o1 v f1 + () 2 f s k ? rf p o ?? ---------------------------------------- -1 d min ? () = (24) where d min d max v dc min v dc max -------------------- - ? = (25) n l1 min l 1 p o 1k rf + () v o1 b sat a e --------------------------------------- - 10 6 = turns () 26 () i ln () rms i o n () 3k rf 2 + () 3 --------------------------- - = (27) v dn () v dc max n sn () n p ------------- = (28) i dn () rms i on () 3k rf 2 + () d max 3 ------------- - = (29)
AN4134 application note 6 ?2002 fairchild semiconductor corporation the ripple current should be equal to or smaller than the ripple current specification of the capacitor. the voltage ripple on the n-th output is given by where c o(n) is the capacitance and r c(n) is the effective series resistance (esr) of the n-th output capacitor. sometimes it is impossible to meet the ripple specification with a single output capacitor due to the high esr of the electrolytic capacitor. then, additional lc filter (post filter) can be used. when using additional lc filter, be careful not to place the corner frequency too low. if the corner frequency is too low, it may make the system unstable or limit the control bandwidth. it is proper to set the corner frequency of the filter to be around 1/10 to 1/5 of the switching frequency. (12) step-12 : design the reset circuit. (a) auxiliary winding reset : for auxiliary winding reset, the maximum voltage and rms current of the reset diode are given by (b) rcd reset : for rcd reset, the maximum voltage and rms current of the reset diode are given by the power loss of the snubber network in normal operation is obtained as where v sn is the snubber capacitor voltage in normal operation, r sn is the snubber resistor, n is n p / n s1 and c oss is the ouput capacitance of the mosfet. based on the power loss, the snubber resistor with proper rated wattage should be chosen. the ripple of the snubber capacitor voltage in normal operation is obtained as in general, 5-10% ripple is practically reasonable. figure 8. snubber capacitor voltage (13) step-13 : design the feed back loop. since fps employs current mode control as shown in figure 9, the feedback loop can be simply implemented with a one pole and one zero compensation circuit. figure 9. control block diagram for continuous conduction mode (ccm) operation, the control-to-output transfer function of forward converter using fps is given by i cn () rms k rf i on () 3 --------------------- - = (30) ? v on () i on () k rf ? 4c on () f s -------------------------- 2 k rf i on () r cn () + = (31) v dreset v dc max 1 n r n p ------ - + ?? ?? = (32) i dreset rms v dc min d max l m f s --------------------------------- - d max 3 ------------- - =33 () v dr v dc max v sn + = (34) i dr rms v dc min d max l m f s --------------------------------- - d max 3 ------------- - = (35) loss sn v sn 2 r sn ----------- - 1 2 -- - nv o1 () 2 l m f s -------------------- - 2nv o1 v sn l m c oss ? --------------------------- - ? == 36 () ? v sn v sn d max c sn r sn f s ------------------------ = (37) vds v dc v sn t 0 t 3 t 2 t 1 t 4 v sn sn v ? v o1 r d i d r bias r 1 r 2 b i bias c b v fb 1:1 fps v o1 ' c f r f 431 i pk mosfet current l p1
application note AN4134 7 ?2003 fairchild semiconductor corporation and r l is the effective total load resistance of the controlled output defined as v o1 2 /p o .when the converter has more than one output, the dc and low frequency control-to-output transfer function are proportional to the parallel combination of all load resistance, adjusted by the square of the turns ratio. therefore, the effective total load resistance is used in equation (38) instead of the actual load resistance of v o1 . the voltage-to-current conversion ratio of fps, k is defined as where i pk is the peak drain current and v fb is the feedback voltage for a given operating condition. figure 10 shows the variation of control-to-output transfer function for a ccm forward converter according to the load. since a ccm forward converter has inherent good line regulation, the transfer function is independent of input voltage variation. while the system pole together with the dc gain changes according to the load condition. the feedback compensation network transfer function of figure 9 is obtained as as can be seen in figure 10, the worst case in designing the feedback loop for a ccm forward converter is the full load condition. therefore, by designing the feedback loop with proper phase and gain margin in low line and full load condition, the stability all over the operation ranges can be guaranteed. the procedure to design the feedback loop is as follows: (a) determine the crossover frequency ( f c ). when an additional lc filter (post filter) is employed, the crossover frequency should be placed below 1/3 of the corner frequency of the post filter, since it introduces -180 degrees phase drop. never place the crossover frequency beyond the corner frequency of the post filter. if the crossover frequency is too close to the corner frequency, the controller should be designed to have enough phase margin more than about 90 degrees when ignoring the effect of the post filter. (b) determine the dc gain of the compensator ( w i /w zc ) to cancel the control-to-output gain at f c . (c) place compensator zero ( f zc ) around f c /3. (d) place compensator pole ( f pc ) above 3 f c . figure 10. ccm forward converter control-to-output transfer function variation according to the load figure 11. compensator design when determining the feedback circuit component, there are some restrictions as follows. (a) the capacitor connected to feedback pin ( c b ) is related to the shutdown delay time in an overload situation as where v sd is the shutdown feedback voltage and i delay is the shutdown delay current. these values are given in the data sheet. in general, 10~100 ms delay time is proper for most practical applications. in some cases, the bandwidth may be limited due to the required delay time in over load protection. (b) the resistor r bias and r d used together with opto-coupler and the ka431 should be designed to provide proper operat- ing current for the ka431 and to guarantee the full swing of the feedback voltage of the fps. in general, the minimum cathode voltage and current for ka431 is 2.5v and 1ma, respectively. therefore, r bias and r d should be designed to satisfy the following conditions. g vc o1 ? fb ? --------- k r l n p n s1 --------- 1sw z ? + 1s +w p ? ----------------------- - ?? ? == 38 () where w z 1 r c1 c o1 ------------------- -, w p 1 r l c o1 ----------------- = = k i pk v fb ---------- i lim 3 -------- = = (39) ? fb ? o1 --------- - w i s ----- 1s +w zc ? 11 +w pc ? -------------------------- - ? = (40) where w i r b r 1 r d c f s -------------------------- , w zc 1 r f r 1 + () c f --------------------------------- , w pc 1 r b c b --------------- = = = 0 db 20 db -20 db -40 db 40 db 10hz 100hz 10khz 1khz 1hz 100khz heavy load light load f p f p f z 0 db 20 db -20 db -40 db 40 db 10hz 100hz 10khz 1khz 1hz 100khz control to output f p f z compensator loog gain t f zc f pc f c w i /w zc t delay v sd 3 ? () = c b ? i delay ? (41)
AN4134 application note 8 ?2003 fairchild semiconductor corporation where v op is opto-diode forward voltage drop, which is typically 1v and i fb is the feedback current of fps, which is typically 1ma. for example, r bias <1k ? and r d <1.5k ? for v o1 =5v. v o v op ? 2.5 ? r d -------------------------------------- i fb > (42) v op r bias ------------- -1ma > (43)
application note AN4134 9 ?2002 fairchild semiconductor corporation - summary of symbols - a w : window area of the core in mm 2 ae : cross sectional area of the core in mm 2 b sat : saturation flux density in tesla. ? b : maximum flux density swing in tesla in normal operation c o : capacitance of the output capacitor. d max : maximum duty cycle ratio e ff : estimated efficiency f l : line frequency f s : switching frequency i ds peak : maximum peak current of mosfet i ds rms : rms current of mosfet i lim : fps current limit level. i sec(n) rms : rms current of the n-th secondary winding i d(n) rms : maximum rms current of the rectifier diode for the n-th output i c(n) rms : rms ripple current of the n-th output capacitor i o : output load current k l(n) : load occupying factor for n-th output k rf : current ripple factor l m : transformer primary side inductance loss sn : power loss of the snubber network in normal operation n p min : the minimum number of turns for the transformer primary side to avoid saturation n p : number of turns for primary side n r : number of turns for reset winding n s1 : number of turns for the reference output p o : maximum output power p in : maximum input power r c : effective series resistance (esr) of the output capacitor. r sn : snubber resistor r l : output load resistor v line min : minimum line voltage v line max : maximum line voltage v dc min : minimum dc link voltage v dc max : maximum dc line voltage v ds nom : maximum nominal mosfet voltage v o1 : output voltage of the reference output. v f1* : diode forward voltage drop of the reference output. v cc* : nominal voltage for vcc v fa : diode forward voltage drop of vcc winding ? v dc max : maximum dc link voltage ripple v d(n) : maximum voltage of the rectifier diode for the n-th output ? v o(n) : output voltage ripple of the n-th output v sn : snubber capacitor voltage in normal operation ? v sn : snubber capacitor voltage ripple v sn max : maximum snubber capacitor voltage during transient or over load situation v ds max : maximum voltage stress of mosfet
AN4134 application note 10 ?2003 fairchild semiconductor corporation appendix. design example using fps design assistant target system : pc power supply - input : universal input (90v-265vrms) with voltage doubler - output : 5v/15a, 3.3v/10a, 12v/6a by choi for forward converter with reset winding blu e c e ll is th e input param e t e rs r e d c e ll r e d c e ll r e d c e ll r e d c e ll is th e output param e t e rs 1. d e fin e sp e cifications of th e smps 1. d e fin e sp e cifications of th e smps 1. d e fin e sp e cifications of th e smps 1. d e fin e sp e cifications of th e smps minimum lin e voltag e (v_lin e .m in) 180 v.rms maximum lin e voltag e (v_lin e .max) 265 v.rms lin e fr e qu e ncy (fl) 60 hz vo vo vo vo io io io io po po po po kl kl kl kl 1st output for f ee dback 5 v 15 a 75 75 75 75 w w w w42 42 42 42 % % % % 2nd output 3.3 v10 a 33 33 33 33 w w w w18 18 18 18 % % % % 3rd output 12 v6 a 72 72 72 72 w w w w40 40 40 40 % % % % 4th output 0 v 0 a 0 0 0 0w w w w0 0 0 0% % % % maximum output po we r (po) = maximum output po we r (po) = maximum output po we r (po) = maximum output po we r (po) = 180.0 180.0 180.0 180.0 w w w w estimat e d e ffici e ncy (eff) 70 % maximum input po we r (pin) = maximum input po we r (pin) = maximum input po we r (pin) = maximum input po we r (pin) = 257.1 257.1 257.1 257.1 w w w w 2. d e t e rmin e dc link capacitor and th e dc voltag e rang e 2. d e t e rmin e dc link capacitor and th e dc voltag e rang e 2. d e t e rmin e dc link capacitor and th e dc voltag e rang e 2. d e t e rmin e dc link capacitor and th e dc voltag e rang e dc link capacitor 235 uf dc link voltag e rippl e = dc link voltag e rippl e = dc link voltag e rippl e = dc link voltag e rippl e =29 29 29 29 v v v v minimum dc link voltag e = minimum dc link voltag e = minimum dc link voltag e = minimum dc link voltag e =226 226 226 226 v v v v maximum dc link voltag e = maximum dc link voltag e = maximum dc link voltag e = maximum dc link voltag e =375 375 375 375 v v v v 3. d e t e rmin e th e maximum duty ratio (dmax) 3. d e t e rmin e th e maximum duty ratio (dmax) 3. d e t e rmin e th e maximum duty ratio (dmax) 3. d e t e rmin e th e maximum duty ratio (dmax) maximum duty ratio 0.4 turns ratio (np/nr) 1 > maximum nominal mosfet voltag e = maximum nominal mosfet voltag e = maximum nominal mosfet voltag e = maximum nominal mosfet voltag e =750 750 750 750 v v v v 4. d e t e rmin e th e rippl e factor of th e output inductor curr e nt 4. d e t e rmin e th e rippl e factor of th e output inductor curr e nt 4. d e t e rmin e th e rippl e factor of th e output inductor curr e nt 4. d e t e rmin e th e rippl e factor of th e output inductor curr e nt output inductor curr e nt rippl e factor 0.15 maximum p e ak drain c urr e nt = maximum p e ak drain c urr e nt = maximum p e ak drain c urr e nt = maximum p e ak drain c urr e nt = 3.27 3.27 3.27 3.27 a a a a rms drain curr e nt = rms drain curr e nt = rms drain curr e nt = rms drain curr e nt = 1.81 1.81 1.81 1.81 a a a a curr e nt limit of fps 4 a 5. d e t e rmin e prop e r cor e and minimum primary turns for transform e r 5. d e t e rmin e prop e r cor e and minimum primary turns for transform e r 5. d e t e rmin e prop e r cor e and minimum primary turns for transform e r 5. d e t e rmin e prop e r cor e and minimum primary turns for transform e r s w itching fr e qu e ncy of fps (khz) 67 khz maximum flux d e nsity s w ing 0.32 t -- > -- > -- > -- > eer2834 eer2834 eer2834 eer2834 estimat e d a p valu e of cor e = estimat e d a p valu e of cor e = estimat e d a p valu e of cor e = estimat e d a p valu e of cor e = 9275 9275 9275 9275 mm mm mm mm 4 4 4 4 a p=12470 a p=12470 a p=12470 a p=12470 cross s e ctional ar e a of cor e ( ae )86mm 2 ae =86 ae =86 ae =86 ae =86 minimum primary turns = minimum primary turns = minimum primary turns = minimum primary turns = 49.0 49.0 49.0 49.0 t t t t aw =145 aw =145 aw =145 aw =145 fps design assistant ver.1.0 0.67 0.67 0.67 0.67 i ? o i o rf i i k 2 ? = t s dt s
application note AN4134 11 ?2002 fairchild semiconductor corporation 6. d e t e rmin e th e numn e r of turns for e ach outputs 6. d e t e rmin e th e numn e r of turns for e ach outputs 6. d e t e rmin e th e numn e r of turns for e ach outputs 6. d e t e rmin e th e numn e r of turns for e ach outputs vo vo vo vo vf vf vf vf # of turns # of turn s # of turn s # of turn s vcc (us e vcc start voltag e ) vcc (us e vcc start voltag e ) vcc (us e vcc start voltag e ) vcc (us e vcc start voltag e ) 15 v1.2 v 3.6 3.6 3.6 3.6 => 4 4 4 4t t t t 1st output for f ee dback 1st output for f ee dback 1st output for f ee dback 1st output for f ee dback 5v 0.4v 3 => 3 3 3 3t t t t 2nd output 2nd output 2nd output 2nd output 3.3 v 0.4 v 2.06 2.06 2.06 2.06 => 2 2 2 2t t t t 3rd output 3rd output 3rd output 3rd output 12 v0.5 v 6.94 6.94 6.94 6.94 => 7 7 7 7t t t t 4th output 4th output 4th output 4th output 0v 0v 0 0 0 0 => 0 0 0 0t t t t vf : for w ard voltag e drop of r e ctifi e r diod e r e s e t w inding = r e s e t w inding = r e s e t w inding = r e s e t w inding = 50 50 50 50 t t t t primary turns = primary turns = primary turns = primary turns = 50 50 50 50 t t t t -> e nough turns -> e nough turns -> e nough turns -> e nough turns a l valu e (no gap) 2490 nh/t 2 transform e r magn e tizing inductanc e = transform e r magn e tizing inductanc e = transform e r magn e tizing inductanc e = transform e r magn e tizing inductanc e = 6.27499 6.27499 6.27499 6.27499 mh mh mh mh -- > eer2834 eer2834 eer2834 eer2834 7. d e t e rmin e th e w ir e diam e t e r for e ach transform e r w inding 7. d e t e rmin e th e w ir e diam e t e r for e ach transform e r w inding 7. d e t e rmin e th e w ir e diam e t e r for e ach transform e r w inding 7. d e t e rmin e th e w ir e diam e t e r for e ach transform e r w inding diam e t e r diam e t e r diam e t e r diam e t e r parall e l parall e l parall e l parall e l irm s irm s irm s irm s ( a /mm ( a /mm ( a /mm ( a /mm 2 2 2 2 ) ) ) ) primary w inding (np) primary w inding (np) primary w inding (np) primary w inding (np) 0.68 mm 1 t 1.81 1.81 1.81 1.81 a a a a r e s e t w indin g (nr) r e s e t w indin g (nr) r e s e t w indin g (nr) r e s e t w indin g (nr) 0.31 mm 1 t 0.08 0.08 0.08 0.08 a a a a vcc w inding vcc w inding vcc w inding vcc w inding 0.31 mm 1 t 0.10 0.10 0.10 0.10 a a a a 1st output w inding 1st output w inding 1st output w inding 1st output w inding 0.68 mm 4 t 9.5 9.5 9.5 9.5 a a a a 2nd output w inding 2nd output w inding 2nd output w inding 2nd output w inding 0.68 mm 3 t 6.3 6.3 6.3 6.3 a a a a 3rd output w inding 3rd output w inding 3rd output w inding 3rd output w inding 0.68 mm 2 t 3.8 3.8 3.8 3.8 a a a a 4th output w inding 4th output w inding 4th output w inding 4th output w inding 0mm 0 t 0.0 0.0 0.0 0.0 a a a a copp e r ar e a = copp e r ar e a = copp e r ar e a = copp e r ar e a = 33.9262 33.9262 33.9262 33.9262 mm mm mm mm 2 2 2 2 fill factor 0.25 r e quir e d w indo w ar e a r e quir e d w indo w ar e a r e quir e d w indo w ar e a r e quir e d w indo w ar e a 135.705 135.705 135.705 135.705 mm mm mm mm 2 2 2 2 --> eer2834 eer2834 eer2834 eer2834 ( aw =145) ( aw =145) ( aw =145) ( aw =145) 8. d e t e rmin e prop e r cor e and numb e r of turns for inductor (coupl e d inductor) 8. d e t e rmin e prop e r cor e and numb e r of turns for inductor (coupl e d inductor) 8. d e t e rmin e prop e r cor e and numb e r of turns for inductor (coupl e d inductor) 8. d e t e rmin e prop e r cor e and numb e r of turns for inductor (coupl e d inductor) cross s e ctional ar e a of inductor cor e ( a 86 mm 2 --> eer2834 eer2834 eer2834 eer2834 saturation flux d e nsity 0.42 t inductanc e of 1st output (l1) = inductanc e of 1st output (l1) = inductanc e of 1st output (l1) = inductanc e of 1st output (l1) = 5.7 5.7 5.7 5.7 uh uh uh uh minimum turns of l1 = minimum turns of l1 = minimum turns of l1 = minimum turns of l1 = 6.5 6.5 6.5 6.5 t t t t a ctual numb e r of turns for l1 6 => 6 6 6 6t t t t num b e r of turns for l2 = num b e r of turns for l2 = num b e r of turns for l2 = num b e r of turns for l2 = 4 4 4 4 => 4 4 4 4t t t t num b e r of turns for l3 = num b e r of turns for l3 = num b e r of turns for l3 = num b e r of turns for l3 = 14 14 14 14 => 14 14 14 14 t t t t num b e r of turns for l4 = num b e r of turns for l4 = num b e r of turns for l4 = num b e r of turns for l4 = 0 0 0 0 => 0 0 0 0t t t t 9. d e t e rmin e th e w ir e diam e t e r for e ach inductor w inding 9. d e t e rmin e th e w ir e diam e t e r for e ach inductor w inding 9. d e t e rmin e th e w ir e diam e t e r for e ach inductor w inding 9. d e t e rmin e th e w ir e diam e t e r for e ach inductor w inding diam e t e r diam e t e r diam e t e r diam e t e r parall e l parall e l parall e l parall e l irm s irm s irm s irm s ( a /mm ( a /mm ( a /mm ( a /mm 2 2 2 2 ) ) ) ) winding for l1 winding for l1 winding for l1 winding for l1 0.68 mm 5 t 15.1 15.1 15.1 15.1 a a a a winding for l2 winding for l2 winding for l2 winding for l2 0.68 mm 3 t 10.0 10.0 10.0 10.0 a a a a winding for l3 winding for l3 winding for l3 winding for l3 0.68 mm 2 t 6.0 6.0 6.0 6.0 a a a a winding for l4 winding for l4 winding for l4 winding for l4 0mm 0 t 0.0 0.0 0.0 0.0 a a a a copp e r ar e a = copp e r ar e a = copp e r ar e a = copp e r ar e a = 25.4089 25.4089 25.4089 25.4089 mm mm mm mm 2 2 2 2 fill factor 0.25 r e quir e d w indo w ar e a r e quir e d w indo w ar e a r e quir e d w indo w ar e a r e quir e d w indo w ar e a 101.636 101.636 101.636 101.636 mm mm mm mm 2 2 2 2 --> eer2834( aw =145) eer2834( aw =145) eer2834( aw =145) eer2834( aw =145) 10. d e t e rmin e th e r e ctifi e r diod e s in th e s e condary sid e 10. d e t e rmin e th e r e ctifi e r diod e s in th e s e condary sid e 10. d e t e rmin e th e r e ctifi e r diod e s in th e s e condary sid e 10. d e t e rmin e th e r e ctifi e r diod e s in th e s e condary sid e r e v e rs e voltag e r e v e rs e voltag e r e v e rs e voltag e r e v e rs e voltag e rms curr e nt rms curr e nt rms curr e nt rms curr e nt vcc diod e vcc diod e vcc diod e vcc diod e 55 55 55 55 v v v v0.10 0.10 0.10 0.10 a a a a -->uf400 3 -->uf400 3 -->uf400 3 -->uf400 3 1st output diod e 1st output diod e 1st output diod e 1st output diod e 22 22 22 22 v v v v9.5 9.5 9.5 9.5 a a a a -->mbr3060pt -->mbr3060pt -->mbr3060pt -->mbr3060pt 2nd output diod e 2nd output diod e 2nd output diod e 2nd output diod e 15 15 15 15 v v v v6.3 6.3 6.3 6.3 a a a a -->mbr3045pt -->mbr3045pt -->mbr3045pt -->mbr3045pt 3rd output diod e 3rd output diod e 3rd output diod e 3rd output diod e 52 52 52 52 v v v v3.81 3.81 3.81 3.81 a a a a -->mbr20h100ct -->mbr20h100ct -->mbr20h100ct -->mbr20h100ct 4th output diod e 4th output diod e 4th output diod e 4th output diod e 0 0 0 0v v v v0.00 0.00 0.00 0.00 a a a a 8.30 8.30 8.30 8.30 #div/0! #div/0! #div/0! #div/0! 9.22 9.22 9.22 9.22 8.30 8.30 8.30 8.30 5.83 5.83 5.83 5.83 5.25 5.25 5.25 5.25 #div/0! #div/0! #div/0! #div/0! 4.98 4.98 4.98 4.98 1.04 1.04 1.04 1.04 1.33 1.33 1.33 1.33 6.56 6.56 6.56 6.56
AN4134 application note 12 ?2003 fairchild semiconductor corporation 11. d e t e rmin e th e output capacitor 11. d e t e rmin e th e output capacitor 11. d e t e rmin e th e output capacitor 11. d e t e rmin e th e output capacitor esr esr esr esr curr e nt curr e nt curr e nt curr e nt voltag e voltag e voltag e voltag e rippl e rippl e rippl e rippl e rippl e rippl e rippl e rippl e 1st output capacitor 1st output capacitor 1st output capacitor 1st output capacitor 4400 uf 20 m ? 1.3 1.3 1.3 1.3 v v v v0.09 0.09 0.09 0.09 v v v v 2nd output capacitor 2nd output capacitor 2nd output capacitor 2nd output capacitor 4400 uf 20 m ? 0.9 0.9 0.9 0.9 v v v v0.06 0.06 0.06 0.06 v v v v 3rd output capacitor 3rd output capacitor 3rd output capacitor 3rd output capacitor 2000 uf 60 m ? 0.5 0.5 0.5 0.5 v v v v0.11 0.11 0.11 0.11 v v v v 4th output capacitor 4th output capacitor 4th output capacitor 4th output capacitor 0uf 0m ? 0.0 0.0 0.0 0.0 v v v v #### #### #### #### v v v v 12. d e sign th e r e s e t circuit 12. d e sign th e r e s e t circuit 12. d e sign th e r e s e t circuit 12. d e sign th e r e s e t circuit r e s e t diod e rms curr e nt r e s e t diod e rms curr e nt r e s e t diod e rms curr e nt r e s e t diod e rms curr e nt 0.08 0.08 0.08 0.08 a a a a maximum voltag e of r e s e t diod e maximum voltag e of r e s e t diod e maximum voltag e of r e s e t diod e maximum voltag e of r e s e t diod e 750 750 750 750 v v v v -->uf4007 -->uf4007 -->uf4007 -->uf4007 13. d e sign f ee dback control loop 13. d e sign f ee dback control loop 13. d e sign f ee dback control loop 13. d e sign f ee dback control loop control-to-output dc gain = control-to-output dc gain = control-to-output dc gain = control-to-output dc gain = 3 3 3 3 control-to-output z e ro = control-to-output z e ro = control-to-output z e ro = control-to-output z e ro = 1,809 1,809 1,809 1,809 hz hz hz hz control-to-output pol e = control-to-output pol e = control-to-output pol e = control-to-output pol e = 261 261 261 261 hz hz hz hz volta g e divid e r r e sistor (r1) 5 ? volta g e divid e r r e sistor (r2) 5 ? opto coupl e r diod e r e sistor (rd ) 1 ? 431 bias r e sistor (rbias) 1.2 ? f ee back pin ca pacitor (cb) = 10 nf f ee dback capacitor (cf) = 100 nf f ee dback r e sistor (rf) = 1 ? f ee dback int e grator gain (fi) = f ee dback int e grator gain (fi) = f ee dback int e grator gain (fi) = f ee dback int e grator gain (fi) = 955 955 955 955 hz hz hz hz f ee dback z e ro (fz) = f ee dback z e ro (fz) = f ee dback z e ro (fz) = f ee dback z e ro (fz) = 265.393 265.393 265.393 265.393 hz hz hz hz f ee dback pol e (f p) = f ee dback pol e (f p) = f ee dback pol e (f p) = f ee dback pol e (f p) = 5307.86 5307.86 5307.86 5307.86 hz hz hz hz 16 9.80783 36 45 16 # -86.7 # 25 9.78487 32 41 25 # -84.9 # 40 9.7248 28 37 40 # -81.9 # 63 9.58236 24 33 63 # -77.3 # 100 9.24037 20 29 100 # -70.4 # 160 8.46816 17 25 160 # -60.6 # 250 7.07174 14 21 250 # -49.4 # 400 4.77208 13 17 400 # -37.8 # 630 1.96652 12 14 630 # -29.6 # 1000 -0.9856 11 10 1000 # -25.5 # 1600 -3.5451 11 7.3 1600 # -26.2 # 2500 -5.2263 10 5.1 2500 # -31.3 # 4000 -6.2187 9.2 3 4000 # -40.8 # 6300 -6.6721 7.3 0.6 6300 # -52.3 # 10000 -6.8719 4.5 -2 #### # -63.5 # 16000 -6.9549 1.1 -6 #### # -72.6 # 25000 -6.9867 -3 -10 #### # -78.6 # 40000 -7.0002 -6 -13 #### # -82.8 # 63000 -7.0054 -10 -17 #### # -85.4 # 100000 -7.0075 -14 -21 #### # -87.1 # capacitanc e capacitanc e capacitanc e capacitanc e v o r d i d r bia s r 1 r 2 b i bias c b v fb 1: 1 fps v o ' c f r f 43 1 -4 0 -2 0 0 20 40 60 10 100 1000 10000 100000 gain (db) co ntorl-to -outp ut co mp e nsator t -12 0 -9 0 -6 0 -3 0 0 10 100 1 000 10 000 100 000 phas e (d e gr ee )
application note AN4134 13 ?2003 fairchild semiconductor corporation design summary ? for the fps, fs7m0880 is chosen. this device has a fixed switching frequency of 67khz. ? to limit the current, a 10 ohm resistor (ra) is used in series with the vcc diode. ? the control bandwidth is 6khz. since the crossover frequency is too close the corner frequency of the post filter (additional lc filter), the controller is designed to have enough phase margin of 120 degrees when ignoring the effect of the post filter. figure 12 shows the final schematic of the forward converter designed by fps design assistant figure 12. the final schematic of the forward converter ka1m0280rb,ka1m0380rb,ka1l0380rb,ka1h0680b,ka1m0680b,ka1h0680rfb,ka1m0680rb,ka1m0880b,ka1m0 880bf,ka1m0880d,ka5h0280r,ka5m0280r,ka5h0380r,ka5m0380r,ka5l0380r,ka5p0680c,fs7m0680,fs7m0880 np n s1 + v dc - ac li ne d r1 c o1 drain vcc gnd fb fs7m0880 ntc fus e r l1 c l1 line filter c l2 n a d a r a c a ka431 817a 10 r bias r 1 r 2 r f c f gbu606 v o1 l 1 c b 2c dc n s2 d r2 v o2 l 2 d f2 d f1 c o2 2c dc n on-doubled doubled d reset 5k 5k 5v 3.3v n s2 v o3 d f3 c o3 nr d r3 l 3 12v 1.2k 1k 2200uf 2 2200uf 2 1000uf 2 mbr3060pt mbr3045pt mbr120h100ct r st art s/s css 1uf uf4007 uf 4003 22uf 560k 10nf 470uf 470uf 1k 100nf 1m 100nf 100nf l p1 c p1 470uf l p2 c p2 1000uf 1.2uh 1.2uh r d
AN4134 application note 3/24/04 0.0m 002 ? 2003 fairchild semiconductor corporation disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corproation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com by hang-seok choi / ph. d fps application group / fairchild semiconductor phone : +82-32-680-1383 facsimile : +82-32-680-1317 e-mail : hschoi@fairchildsemi.co.kr

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